November 2012
Chris Scanlan, vice president, product management, Deca Technologies Inc.


Fan-Out Wafer-Level Packaging (FOWLP) or fan-out technology has held promise for a number of years; primarily as a means of packaging semiconductor devices with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP). With FOWLP technology, die are embedded in a molded panel, and I/Os are then redistributed over the larger effective surface area using conventional WLCSP techniques. The packages are then singulated and attached directly to a printed circuit board (PCB) or low-cost substrate. This technology provides one of the smallest and lightest possible package form factors; enables more I/Os for a given pitch with excellent electrical properties; and eliminates the need for custom substrates used in flip chip or wirebond Ball Grid Array (BGA) packages. Despite its promise, widespread adoption of FOWLP packaging has been limited largely by cost and yield issues. The requirement for high die placement accuracy when forming the molded panel restricts throughput at the die pick-and-place operation, leading to high process costs. Die drift, or movement during panel molding, limits via and RDL design rules and ultimately can result in yield loss when the drift is excessive. Managing or overcoming die offset is one of the keys to making FOWLP competitive with other package formats.

This paper describes an approach to FOWLP that allows die offset to increase by an order of magnitude compared with conventional methods. Using a novel Adaptive Patterning* technology, real-time designs are created for each package within each panel during the manufacturing process. After panelization, the position of each die within each molded panel is precisely measured. Information is fed into a proprietary auto-routing design tool on a per panel basis. The resulting pattern layers are then issued to a lithography system which dynamically implements the unique design on a per panel basis. Dynamic layers include various design features such as vias or redistribution layers (RDL).
The ability of adaptive patterning to correct for deviations in die location can result in both improved yield and higher panelization throughput, thereby enabling the industry to finally realize the cost, flexibility, and form factor benefits of FOWLP. In the paper, adaptive patterning examples will be presented and the benefits and limitations of the technology will be discussed.

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This paper was originally published by the SMTA for IWLPC 2012, and was presented at the DoubleTree Hotel in San Jose on November 8, 2012