Technology Papers

Conference and Publication Listing


Nepcon Japan 2024Jan ’24Patterning Technology that Realizes a Chiplet Structure and the Latest Laser Direct Imaging Lithography (LDI) Technology Capable of 2um L/SCliff S. et. al.
Chiplet Summit 2024Jan ’24Choosing from the Bewildering Menu of Advanced Packaging OptionsCraig B., et. al.


EPTC 2023Dec ’23Deca & ASE M-Series Bridge Die Compensation & Adaptive Patterning in a Multi-Die Module in 600 mm Format Cliff S. et. al.
IMAPS Az Chapter SeminarNov ’23Achieving High-Density Die-to-Die Integration with Adaptive Pad Stacks on a Molded Embedded Bridge Die InterposerCliff S. et. al.
IMAPS Symposium 2023Oct’23Gen 2 M-Series Fan-Out for Chiplet Integration, UCIe, and HBM3Craig B., et. al.
IMAPS FL WorkshopSept ’23Ultra-High-Density Integration of Chiplets using Adaptive Patterning for High Performance ComputingCliff S. et. al.
ECTC 2023May ’23Integrating Chiplets using Chips First Ultra-High-Density Fan-out with Maskless Laser Direct Imaging and Adaptive Patterning for High Performance Computing Benedict S.J., et al.
Synopsys SNUG Silicon Valley 2023Mar’23Next-gen Fan-out Technology & EDA for Multi-Die IntegrationCraig B., et. al.
IMAPS DPC 2023Mar’23Scaling Interconnect Densities​ Meeting the Growing Demand for Chiplet Integration​Robin D., et. al.
IMAPS DPC 2023Mar’23Squaring Off with M-Series Fan-Out Technology​Cliff S. et. al.
SMTA Wafer Level Packaging Symposium ’23Feb’23Large Heterogenous Integration Devices ​Drive Large Panel Fan-outBenedict S.J., et al.
Chiplet Summit 2023Jan’23Next-gen Fan-out Interconnect for Chiplets and BeyondCraig B., et. al.


EPTC 2022Dec ’22Mask-less Laser Direct Imaging & Adaptive Patterning Solution for Fan-Out Heterogeneous Integration on 600mmCliff S. et. al.
EPTC 2022Dec ’22Reducing the Thermal Budget in Low-Temperature Polyimide Dielectric Cure for Laser Direct Image Patterning in Advanced Backend ApplicationsCliff S. et. al.
SMTA Intl Electronics Manufacturing Conference ’22Nov’22Heterogenous Integration using Fan-out Wafer-level Packaging (FOWLP) Technology to Produce High Performance and Low-Cost Multi-Chip Modules Tim O., et. al.
IMAPS Symposium 2022Oct ’22Bridging the Interconnect Gap for High Performance Computing using an M-Series Embedded Cache InterposerBenedict S.J., et al.
ECTC 2022May ’22Evolution of Interconnect EDA for Chiplets and Heterogeneous IntegrationCraig B.
ECTC 2022May ’22Harnessing the power of 4nm silicon with Gen 2 M-Series™ Fan-out and Adaptive Patterning® enabling ultra-high-density 20µm device bond pad pitchRobin D., et. al.
IMAPS DPC 2022Mar’22Mask-less Laser Direct Imaging & Adaptive Patterning Solution for Fan-Out Heterogeneous IntegrationCliff S. et. al.
IMAPS DPC 2022Mar’22Scaling Up while Scaling Down ​with M-Series™ Fan-out & Adaptive Patterning®Tim O., et. al.
IMAPS DPC 2022Mar’22High-density Fan-Out Chip on Substrate using M-Series™ and Adaptive Patterning®  TechnologyRobin D., et. al.
SMTA Wafer Level Packaging Symposium ’22Feb’22Chips First or Chips Last? – ​Answering the Key Questions ​for the Adoption of Heterogenous IntegrationBenedict S.J., et al.


Raytheon 3DHI WorkshopNov’21Ultra-high-density Embedded Die Interposers for 3D Heterogenous Integration created with M-Series Fan-out and Adaptive Patterning TechnologyBenedict S.J., et al.
IMAPS DPC 2021Apr’21Setting the 600mm Large Panel Fan-Out Standard with M-Series™Cliff S. et. al.
IMAPS DPC 2021Apr’21New Adaptive Patterning Techniques for the Chiplet EraCraig B., et. al.
IMAPS DPC 2021Apr’21Using Deca’s Adaptive Patterning to Win the Chiplet Integration Race with Siemens EDA and ASERobin D., et. al.
ECTC 2021June’21Deca & Cadence Breakthrough Heterogeneous Integration Barriers with Adaptive Patterning™ Ed H., et. al.
ECTC 2021June’21Scaling M-Series™ for ChipletsCliff S. et. al.

Published Articles

Chip Scale Review – Nov 2022Nov’22Large-panel fan-out perspective on cost, yield, and capabilityCliff S. et. al.
Semiconductor Review – Dec 2020Dec’20Deca: Rewriting the rules of chip interconnectionRichmond S.
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