Authors: Robin Gabriel, Jan Kellar, Keith Felton, Ian Gabbitas, John Hunt, Lihong Cao


As the need for chiplet integration becomes more prevalent in industry, the current standard of silicon interposers is not sustainable for broad adoption. Among the top technologies competing in the race are embedded bridge chip structures, chips-last fan-out, and chips-first fan-out. Deca’s M-SeriesTM, a fully organic chips-first planar structure, promises a new way to achieve equivalent density to benchmark high density interconnects without the need for complex structures and processes. Deca Technologies, Siemens EDA, and ASE Group (Advanced Semiconductor Engineering) formed a collaboration to design, verify, build, and perform analysis on an M-series chiplet test vehicle. For this proof of concept, a 10-die chiplet package was designed using Siemens EDA’s Xpedition high density advanced packaging (HDAP) technologies. Siemens EDA’s Calibre was then used to perform verification and signoff. With design, verification, and signoff complete, follow up plans are to build a test vehicle with ASE for physical characterization.

Deca’s technology has surpassed other fan-out technologies in the chiplet integration race with Adaptive Patterning; achieving significantly higher density for both vias and wiring traces while enabling designs with the tightest device bond pad pitch. The planar surface of M-Series enables trace width and spacing of 2μm and Adaptive Patterning makes possible a smaller copper stud size (competitors add an additional copper layer to increase the size) yielding a 20μm copper stud pitch. In addition to an 80% reduction in the area required for a set number of copper studs (device IO), this technology also provides the highest integrity electrical connections with superior via contact area. When compared to competing technologies, greater than a 200% increase in via contact area can be achieved for the same bond pad pitch. This test vehicle design highlights the fact that Adaptive Patterning provides a compelling solution over existing competitive technologies in the chiplet integration race.

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