Debbie Claire Sanchez, Deca Technologies
Fan-Out Wafer-Level Packaging (FOWLP) is poised to become a mainstream packaging technology, providing a means of packaging semiconductor chips with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP), while delivering size and performance benefits similar to WLCSPs. FOWLP can also be used for multi-chip integration to create system-in-packages and thus can compete in applications previously targeted for 2.5D. These benefits have led many in the industry to predict a significant compound annual growth rate for FOWLP over the next few years. Challenges that remain with this technology include developing the infrastructure necessary to support growing industry demand, controlling costs, driving higher yields, and developing smaller linewidths to support high density wiring applications.
This paper describes a unique chips “face-up” approach to panelization, the process in which die are embedded in mold compound to effectively grow the die surface and to create a panel for supporting RDL build-up. In this approach, die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool to achieve high throughput and low cost. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs, which provide current pathways from the chip IOs to the mold compound surface. A high speed optical scanner is used to inspect the Cu studs protruding through the mold compound, to determine the actual position of every die on the panel. This information is fed into a proprietary design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. The result is a panelization process which can deliver high yielding panels with high throughput and low cost and with a planar surface capable of supporting high density RDL wiring.
This paper details challenges and benefits of this chips face-up approach and describes Adaptive Patterning strategies used to compensate for die displacement in the molded panel and thus achieve high panel yield.