Published in: 2021 IEEE 71st Electronic Components and Technology Conference (ECTC)

Authors: Edward Hudson, Dan Baldwin, Tim Olson, Craig Bishop, Jan Kellar, Robin Gabriel

Abstract: Achieving the highest performance levels through heterogeneous integration requires innovation throughout the package design, layout, and manufacturing processes. As part of a recent partnership, Cadence and Deca have collaborated on a novel multi-chip(let) high-density RDL packaging solution based on Adaptive Patterning™ technologies. This approach removes several design hurdles for multi-chip(let) ultra-high-density fanout packages while providing a cost-effective alternative to foundry-based solutions. The Adaptive Alignment™ design technique translates and rotates polymer and copper routing layers to align with individual chip(let) locations precisely. Another technique, Adaptive Routing™, allows the designer to create dynamic regions within Cadence Allegro® Package Designer where layout features are automatically generated in real-time to create unit-specific patterns aligned with the actual location of each chip(let) pin. With the freedom to choose any combination of these Adaptive Patterning design methods, the designer is empowered to layout complex multi-chip(let) high-density fan-out packages while being assured that all normal variations in manufacturing can be accommodated based on certified design rules from Deca®. This presentation highlights ultra-high-density RDL layout of single-chip and multi-chip(let) designs using Deca Adaptive Patterning technology embedded in Cadence Allegro Package Designer, Silicon Layout Option. This paper includes showing the Cadence design tool flow for importing user data and configuring the Cadence database for M-Series™ FX fan-out designs.

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