Deca’s Patent Portfolio

Over the years, Deca Technologies have developed an extensive patent portfolio focusing on three main areas of technology namely: Adaptive Patterning®, M-Series, and Autoline. These three technology areas are the pillars enabling Deca’s mission of creating advanced electronic interconnect solutions for the Chiplet Era.

Adaptive Patterning®

Adaptive Routing connecting the shifted
prestratum to the fixed prestratum
(US Patent # 8,656,333)
RDL interconnect structure for multi-die packages
using Adaptive Alignment
(US Patent #10573601)
8,656,333Integrated Circuit Package Auto-Routing
8,799,845Adaptive Patterning for Panelized Packaging
8,826,221Adaptive Patterning for Panelized Packaging
182715Adaptive Patterning for Panelized Packaging
9,040,316Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging with Dynamic Via Clip
9,196,509Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging
ZL
201180001658.9		Adaptive Patterning for Panelized Packaging
11201503242WSemiconductor Device and Method Of Adaptive Patterning for Panelized Packaging
9,397,069Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging with Dynamic Via Clip
9,401,313Automated Optical Inspection of Unit Specific Patterning
9,418,905Adaptive Patterning for Panelized Packaging
9,520,331Adaptive Patterning for Panelized Packaging
9,520,364Front Side Package-Level Serialization for Packages Comprising Unique Identifiers
ZL 201380033254.7Integrated Circuit Package Auto-Routing
9,818,659Multi-Die Package Comprising Adaptive Alignment and Routing
9,887,103Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging
ZL 201380064057.1Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging
10,056,304Automated Optical Inspection of Adaptive Patterning
10,157,803Semiconductor Device and Method of Unit Specific Progressive Alignment
10-1957851Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging with Dynamic Via Clip
10-2016-7035116Semiconductor Device and Method of Adaptive Patterning For Panelized Packaging with Dynamic Via Clip
ZL 201580033193.3Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging with Dynamic Via Clip
1674635Multi-Die Package Comprising Adaptive Alignment and Routing
10-2081684Front-Side Package Level Serialization for Packages Comprising Unique Identifiers
10-2081682Multi-Die Package Comprising Adaptive Alignment and Routing
10573601Semiconductor Device and Method of Unit Specific Progressive Alignment
9,978,655Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging With Dynamic Via Clip
6685301Automated Optical Inspection of Adaptive Patterning
1234252Semiconductor Device and Method of Adaptive Patterning for Panelized Packaging with Dynamic Via Clip
ZL 201580045860.XFront-Side Package Level Serialization for Packages Comprising Unique Identifiers
10-2197228Semiconductor Device and Method of Unit Specific Progressive Alignment

M-Series Patents

Illustration of individual M-Series device package
(US Patent # 8,535,978)
Illustration of a 3D interconnect M-Series package
(US Patent # 9,502,397)
8,535,978Die Up Fully Molded Fan-Out Wafer Level Packaging
8,835,230Fully Molded Fan-Out (Method)
8,922,021Die Up Fully Molded Fan-Out Wafer Level Packaging
8,604,600Fully Molded Fan-Out (device)
9,177,926Semiconductor Device and Method Comprising Thickened Redistribution Layers
ZL 201180008457.XFan Out Wafer Level Package with Transferred Dielectric 
9,269,622Semiconductor Device and Method of Land Grid Array Packaging with Bussing Lines
9,337,086Die Up Fully Molded Fan-Out Wafer Level Packaging
11201404309VDie Up Fully Molded Fan-Out Wafer Level Packaging
11201504442YSemiconductor Device and Method of Land Grid Array Packaging with Bussing Lines
9,502,3973D Interconnect Component for Fully Molded Packages
ZL201210311793.XFully Molded Fan-Out
9,576,919Semiconductor Device and Method Comprising Redistribution Layers 
11201404307TFully Molded Fan-Out
9,613,830Fully Molded Peripheral Package on Package Device
ZL 201280069322.0Die Up Fully Molded Fan-Out Wafer Level Packaging
9,754,835Semiconductor Device and Method Comprising Thickened Redistribution Layers
9,761,571Thermally Enhanced Fully Molded Fan-Out Module
9,831,170Fully Molded Miniaturized Semiconductor Module
10,050,004Fully Molded Peripheral Package on Package Device
I643271Thermally Enhanced Fully Molded Fan-out Module
10201503498XFan Out Wafer Level Package with Transferred Dielectric Film
ZL 201480008489.5 Semiconductor Device and Method of Land Grid Array Packaging with Bussing Lines
10,373,902 B2Fully Molded Miniaturized Semiconductor Module
10,373,870Semiconductor Device and Method of Packaging
1674658Fully Molded Miniaturized Semiconductor Module
I6900443D Interconnect Component for Fully Molded Packages
10-2114563Thermally Enhanced Fully Molded Fan-Out Module
10,672,624Method of Making Fully Molded Peripheral Package on Package Device
10-2127774Fully Molded Miniaturized Semiconductor Module
10,720,417Thermally Enhanced Fully Molded Fan-Out Module
10-2164011Fully Molded Peripheral Package on Package Device
10-2164012Fully Molded Peripheral Package on Package Device
10,818,635Fully Molded Semiconductor Package for Power Devices and Method of Making the Same

Autoline Patents

Illustration comparing VIA profiles cured at one-step
and two-step Rapid Cure
(US Patent # 9,159,574)
Illustration of Travelling Puddle Process
(US Patent # 9,640,495)
Illustration of dual-sided wafer plating jig and cover
(US Patent # 9,464,362)
8,784,621Wafer Carrier Comprising a Variable Aperture Shield 
8,932,443Adjustable Wafer Plating Shield and Method
9,159,547Two Step Method of Rapid Curing a Semiconductor Polymer Layer
9,464,362Magnetically Sealed Wafer Plating Jig System and Method
9,613,912Method of Marking a Semiconductor Package
9,640,495Semiconductor Device Processing Method for Material Removal 
9,653,339Integrated Shielding for Wafer Plating
ZL201280075204.0Magnetically Sealed Wafer Plating Jig System and Method
ZL 201480051294.9Two Step Method of Rapid Curing a Semiconductor Polymer Layer
10,204,803Two Step Method of Rapid Curing a Semiconductor Polymer Layer
I664708Method of Marking a Semiconductor Package
10373913Method of Marking a Semiconductor Package
ZL 201580069079.6Method of Marking a Semiconductor Package
10-2081683Semiconductor Device Processing Method for Material Removal
10600652Semiconductor Device Processing Method for Material Removal
I692023Semiconductor Device Processing Method for Material Removal
8,236,151Substrate Carrier For Wet Chemical Processing
10-2197220Two Step Method of Rapid Curing a Semiconductor Polymer Layer

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