Chapter 6 in: Advances in Embedded and Fan-Out Wafer-Level Packaging Technologies
Authors: Tim Olson, Chris Scanlan
Editors: Beth Keser Ph.D., Steffen Kroehnert
Abstract: This chapter deals with construction, manufacturing process, design features and system integration, adaptive patterning, and applications of M-Series. M-Series utilizes a semiconductor wafer manufacturing environment including advanced lithography, PVD, electroplating, etching, cleaning, and visual inspection methodologies consistent with fabricating wafer-level packaging as well as the final back-end-of-line interconnect layers within semiconductor device fabs. Several different via stack-up options are possible within the M-Series fan-out buildup structure. One of the main challenges that has prevented the widespread adoption of wafer-level fan-out technology is yield loss due to imperfect alignment of fixed lithography masks to shifting devices during manufacturing. For M-Series, Deca Technologies invented a technology called adaptive patterning to overcome the die-shift problem without compromising chip-attach throughput or design rules and to further enable high yield multi-die system-in-package devices. There are several techniques that can be used to generate the per-package lithography patterns: adaptive alignment and adaptive routing.
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