Authors: Craig Bishop, Ryan Bartling, Sean Wang
Abstract: As the industry has evolved to deliver heterogenous integration, chiplets, and high-density interconnect, so has Deca’s Adaptive Patterning™ (AP) technology. Wafer and panel fan-out, fan-out on substrate, and other embedded die interconnect technologies all have inherent natural variations in the manufacturing process, with die-shift typically having the highest impact. Rather than fight variation by using high accuracy, lower throughput equipment, AP takes a different approach and accommodates variation through real-time design-during-manufacturing. First a high-speed optical scanner measures the actual position of each die, next the AP software system generates a unique per-unit lithography pattern adapted to its individual measurement, and finally the specific per-unit patterns are implemented with a single-pass, mask-less lithography system. Techniques such as Adaptive Alignment for single-die, and Adaptive Routing for multi- die integration are used to enable the highest density design rules.
This publication will present two newly developed AP techniques that allow further scaling to high density interconnect. The first, Progressive Adaptive Alignment, extends previous techniques to allow distribution of the die-shift across all layers in the stack-up. Example design studies will be shown to illustrate the advantages for fan-out on substrate and package-on-package (PoP). The second technique, Adaptive Metal Fill, dynamically redesigns power planes, signal planes, and fill metal to account for measured die-shift. Adaptive power planes and signal planes provide robust signal integrity for multi-die integration, while dynamic metal fill optimizes the topography in multi-RDL products, delivering real-time design-for- manufacturing (DFM). An example design study with multiple chiplet-to-chiplet interfaces will explore possible applications and benefits for designs with 2 μm, and finer, lines.
These Adaptive Patterning techniques offer a compelling solution for chiplet integration. Removing traditional fixed photomasks from the equation breaks through conventional barriers to fine-pitch, high density, and high-yield for embedded die structures.
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