B. Rogers, M. Melgo, M. Almonte, S. Jayaraman, C. Scanlan, and T. Olson
Wafer-level chip scale packaging (WLCSP) offers the smallest package form factor and has become a preferred option for the handheld consumer electronics space where portability and increasing functionality are strong drivers. WLCSPs also continue to migrate into other applications requiring small size, high performance, and low cost. However, the thermal mismatch between the silicon chip and the organic printed circuit board (PCB) has limited WLCSPs to relatively small die sizes — usually less than 5×5mm2 — so WLCSP suppliers and users are continually looking for ways to improve reliability and extend the size range of chips that can utilize this unique packaging technology.
Optimizing the solder joint geometry and the WLCSP buildup layer thicknesses are relatively simple but effective ways to improve WLCSP reliability. Important geometric variables to consider include the size of the RDL capture pad and via under the bump on the WLCSP, the size of the WLCSP under bump metallurgy (UBM) pad, and the size of the corresponding pad on the PCB. Thicknesses of the RDL and polymer buildup layers on the WLCSP also can play a significant role. Finally, choice of solder alloy can have a tremendous impact on the board level reliability of the part. Optimizing these factors can lead to performance improvements in thermal cycling and drop, the two key board-level reliability tests that predict the life of the WLCSP.
This paper will present data on the relative impact of solder joint geometry, build-up layer thicknesses, and solder alloy on WLCSP reliability. Board level reliability results on some new solder alloys will be presented, highlighting the relative strengths of these alloys with regard to thermal cycling and drop performance. Finally, the methods learned here will be applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.