November 2013
Boyd Rogers, Ph.D.
Vice President of R&D, Deca Technologies


Fan-Out Wafer-Level Packaging (FOWLP) is finally beginning to gain traction as a means of packaging semiconductor chips with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP). However, despite its promise, widespread adoption of FOWLP has been limited largely by manufacturing and reliability challenges. In particular, discontinuity at the silicon – mold compound edge leads to numerous issues: (1) increased panel warpage; (2) mold flash on top of the die surface, which can produce yield loss; (3) a step between the die and the mold compound, which can result in patterning difficulties; and (4) lower reliability, due to the thermal mismatch between the mold compound and the silicon.

This paper describes a fully molded FOWLP technology which addresses the above issues. In this approach, Cu pillars are fabricated at IO locations on the native semiconductor wafer prior to the panelization process. Then, during panelization, the die is encased on all sides in mold compound, with the Cu pillars providing the current pathways through the mold compound on the front die surface. Finally, buildup processing is performed on the front panel surface with interconnection to the exposed Cu pillars. The benefits of the fully molded structure include: (1) separation of the discontinuity at the die edge from the buildup structure; (2) better panel warpage control due to the balanced material around the die; and (3) improved board level reliability as a result of the molded layer separation between the chip and PCB connections. The end result is a rugged package. This paper details the fully molded FOWLP technology, describes build examples, and provides reliability data validating the approach.

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This paper was originally published by the SMTA for IWLPC 2013, and was presented at the DoubleTree Hotel in San Jose on November 7, 2013