October 2013
Boyd Rogers, Ph.D. vice president of R&D, Deca Technologies
Chris Scanlan, vice president, product management, Deca Technologies


The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

Download PDF

This paper was originally published by IMAPS International and presented at the 46th International Symposium on Microelectronics, October 2, 2013